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1 rev: a date: 1/27/04 sp505 multi?ode serial transceiver ?copyright 2004 sipex corporation the sp505 is a monolithic device that supports eight (8) popular serial interface standards for dte to dce connectivity. the sp505 is fabricated using a low power bicmos process technology, and incorporates a sipex patented (5,306,954) charge pump allowing +5v only operation. seven (7) drivers and seven (7) receivers can be configured via software for any of the above interface modes at any time. the sp505 requires no additional external components for compliant operation for all of the eight (8) modes of operation. all necessary termination is integrated within the sp505 and is switchable when v.35 drivers, v.35 receivers, and v.11 receivers are used. the sp505 can operate as either a dte or dce. additional features with the sp505 include internal loopback that can be initiated in either single-ended or differential modes. while in loopback mode, driver outputs are internally connected to receiver inputs creating an internal signal path convenient for diagnostic testing. this eliminates the need for an external loopback plug. the sp505 also includes a latch enable pin with the driver and receiver address decoder. tri-state ability for the driver and receiver outputs is controlled by supplying a 4-bit word into the address decoder. seven (7) drivers and one (1) receiver in the sp505 include separate enable pins for added convenience. the sp505 is ideal for wan serial ports in networking equipment such as routers, switches, dsu/csu's, and other access devices. sp505 w an multi-mode serial transceiver description... +5v only operation seven (7) drivers and seven (7) receivers driver and receiver tri-state control internal transceiver termination resistors for v.11 and v.35 protocols loopback self-test mode software selectable protocol selection interface modes supported: ? rs-232 (v.28) ? x.21/rs-422 (v.11) ? eia-530 (v.10 & v.11) ? eia-530a (v.10 & v.11) ? rs-449 (v.10 & v.11) ? v.35 (v.35 & v.28) ? v.36 (v.10 & v.11) ? rs-485 (un-terminated v.11) improved esd tolerance for analog i/os high differential transmission rates ? sp505a - 10mbps ? sp505b - over 16mbps compliant to net1/2 and tbr2 physical layer requirements (tuv test report net2/052101/98) (tuv test report ctr2/052101/98) eia-530 wan v .35
2 rev: a date: 1/27/04 sp505 multi?ode serial transceiver ?copyright 2004 sipex corporation specifications t a = +25? and v cc = +4.75v to +5.25v unless otherwise noted. min. typ. max. units conditions logic inputs v il 0.8 volts v ih 2.0 volts logic outputs v ol 0.4 volts i out = ?.2ma v oh 2.4 volts i out = 1.0ma v.28 driver dc parameters outputs open circuit voltage +15 volts per figure 1 loaded voltage +5.0 +15 volts per figure 2 short-circuit current +100 ma per figure 4 power-off impedance 300 ? per figure 5 ac parameters v cc = +5v for ac parameters outputs transition time 1.5 s per figure 6; +3v to -3v instantaneous slew rate 30 v/ s per figure 3 propagation delay t phl 0.5 1 5 s t plh 0.5 1 5 s max.transmission rate 120 230 kbps v.28 receiver dc parameters inputs input impedance 3 7 k ? per figure 7 open-circuit bias +2.0 volts per figure 8 high threshold 1.7 3.0 volts low threshold 0.8 1.2 volts ac parameters v cc = +5v for ac parameters propagation delay t phl 50 100 500 ns t plh 50 100 500 ns absolute maximum ratings these are stress ratings only and functional operation of the device at these ratings or any other above those indicated in the operation sections of the specifications below is not implied. exposure to absolute maximum rating conditions for extended periods of time may affect reliability. v cc ............................................................................+7v input voltages: logic...............................-0.3v to (v cc +0.5v) drivers............................-0.3v to (v cc +0.5v) receivers........................................?5.5v output voltages: logic................................-0.3v to (v cc +0.5v) drivers................................................?5v receivers........................-0.3v to (v cc +0.5v) storage temperature..........................-65?c to +150?c power dissipation.........................................2000mw package derating: ja ....................................................46 ?/w jc ...................................................16 ?/w storage considerations due to the relatively large package size of the 80-pin quad flat-pack, storage in a low humidity environment is preferred. large high density plastic packages are moisture sensitive and should be stored in dry vapor barrier bags. prior to usage, the parts should remain bagged and stored below 40? and 60%rh. if the parts are removed from the bag, they should be used within 48 hours or stored in an environment at or below 20%rh. if the above conditions cannot be followed, the parts should be baked for four hours at 125? in order remove moisture prior to soldering. sipex ships the 80-pin qfp in dry vapor barrier bags with a humidity indicator card and desiccant pack. the humidity indicator should be below 30%rh.
3 rev: a date: 1/27/04 sp505 multi?ode serial transceiver ?copyright 2004 sipex corporation specifications t a = +25? and v cc = +4.75v to +5.25v unless otherwise noted. min. typ. max. units conditions v.28 receiver (continued) ac parameters (cont.) max.transmission rate 120 230 kbps v.10 driver dc parameters outputs open circuit voltage +4.0 +6.0 volts per figure 9 test-terminated voltage 0.9v oc volts per figure 10 short-circuit current +150 ma per figure 11 power-off current +100 a per figure 12 ac parameters v cc = +5v for ac parameters outputs transition time 200 ns per figure 13; 10% to 90% propagation delay t phl 50 100 500 ns t plh 50 100 500 ns max.transmission rate 120 kbps v.10 receiver dc parameters inputs input current ?.25 +3.25 ma per figures 14 and 15 input impedance 4 k ? sensitivity +0.3 volts ac parameters v cc = +5v for ac parameters propagation delay t phl 50 120 250 ns t plh 50 120 250 ns max.transmission rate 120 kbps v.11 driver dc parameters outputs open circuit voltage +5.0 volts per figure 16 test terminated voltage +2.0 volts per figure 17 0.5v oc 0.67v oc volts balance +0.4 volts per figure 17 offset +3.0 volts per figure 17 short-circuit current +150 ma per figure 18 power-off current +100 a per figure 19 ac parameters v cc = +5v for ac parameters outputs transition time 20 ns per figures 21 and 36; 10% to 90% propagation delay t phl 50 85 110 ns per figures 33 and 36, c l = 50pf t plh 50 85 110 ns per figures 33 and 36, c l = 50pf differential skew 10 20 ns per figures 33 and 36, c l = 50pf max.transmission rate per figure 33, c l = 50pf SP505ACF 10 12 mbps f in = 5mhz sp505bcf 16.4 18 mbps f in = 8.2mhz v.11 receiver dc parameters inputs common mode range ? +7 volts sensitivity +0.3 volts
4 rev: a date: 1/27/04 sp505 multi?ode serial transceiver ?copyright 2004 sipex corporation specifications t a = +25? and v cc = +4.75v to +5.25v unless otherwise noted. min. typ. max. units conditions v.11 receiver (continued) dc parameters (cont.) input current ?.25 +3.25 ma per figure 20 and 22 current w/ 100 termination +60.75 ma per figure 23 and 24 input impedance 4 k ? ac parameters v cc = +5v for ac parameters propagation delay t phl 80 110 130 ns per figures 33 and 38; c l = 50pf t plh 80 110 130 ns per figures 33 and 38; c l = 50pf differential skew 20 ns per figure 33; c l = 50pf max.transmission rate per figure 33; c l = 50pf SP505ACF 10 12 mbps f in = 5mhz sp505bcf 16.4 18 mbps f in = 8.2mhz v.35 driver dc parameters outputs open circuit voltage +1.20 volts per figure 16 test terminated voltage +0.44 +0.66 volts per figure 25 offset +0.6 volts per figure 25 source impedance 50 150 ? per figure 27; z s = v 2 /v 1 x 50 short-circuit impedance 135 165 ? per figure 28 ac parameters v cc = +5v for ac parameters outputs transition time 30 40 ns per figure 29; 10% to 90% propagation delay t phl 50 90 110 ns per figures 33 and 36; c l = 20pf t plh 50 90 110 ns per figures 33 and 36; c l = 20pf differential skew 20 30 ns per figures 33 and 36; c l = 20pf max.transmission rate per figure 33; c l = 20pf SP505ACF 10 12 mbps f in = 5mhz sp505bcf 16.4 18 mbps f in = 8.2mhz v.35 receiver dc parameters inputs sensitivity +80 mv source impedance 90 110 ? per figure 30; z s = v 2 /v 1 x 50 short-circuit impedance 135 165 ? per figure 31 ac parameters v cc = +5v for ac parameters propagation delay t phl 80 110 130 ns per figures 33 and 38; c l = 20pf t plh 80 110 130 ns per figures 33 and 38; c l = 20pf differential skew 20 ns per figure 33; c l = 20pf max.transmission rate per figure 33; c l = 20pf SP505ACF 10 12 mbps f in = 5mhz sp505bcf 16.4 18 mbps f in = 8.2mhz transceiver leakage currents driver output 3-state current 100 500 a per figure 32; drivers disabled rcvr output 3-state current 1 10 a dec x = 0000, 0.4v v o 2.4v
5 rev: a date: 1/27/04 sp505 multi?ode serial transceiver ?copyright 2004 sipex corporation other ac characteristics t a = +25? and v cc = +5.0v unless otherwise noted. parameter min. typ. max. units conditions driver delay time between active mode and tri-state mode rs-232/v.28 t pzl ; tri-state to output low 0.70 5.0 sc l = 100pf, fig. 34 & 40; s 1 closed t pzh ; tri-state to output high 0.40 2.0 sc l = 100pf, fig. 34 & 40; s 2 closed t plz ; output low to tri-state 0.20 2.0 sc l = 100pf, fig. 34 & 40; s 1 closed t phz ; output high to tri-state 0.40 2.0 sc l = 100pf, fig. 34 & 40; s 2 closed rs-423/v.10 t pzl ; tri-state to output low 0.15 2.0 sc l = 100pf, fig. 34 & 40; s 1 closed t pzh ; tri-state to output high 0.20 2.0 sc l = 100pf, fig. 34 & 40; s 2 closed t plz ; output low to tri-state 0.20 2.0 sc l = 100pf, fig. 34 & 40; s 1 closed t phz ; output high to tri-state 0.15 2.0 sc l = 100pf, fig. 34 & 40; s 2 closed rs-422/v.11 t pzl ; tri-state to output low 2.80 10.0 sc l = 100pf, fig. 34 & 37; s 1 closed t pzh ; tri-state to output high 0.10 2.0 sc l = 100pf, fig. 34 & 37; s 2 closed t plz ; output low to tri-state 0.10 2.0 sc l = 15pf, fig. 34 & 37; s 1 closed t phz ; output high to tri-state 0.10 2.0 sc l = 15pf, fig. 34 & 37; s 2 closed v.35 t pzl ; tri-state to output low 2.60 10.0 sc l = 100pf, fig. 34 & 37; s 1 closed t pzh ; tri-state to output high 0.10 2.0 sc l = 100pf, fig. 34 & 37; s 2 closed t plz ; output low to tri-state 0.10 2.0 sc l = 15pf, fig. 34 & 37; s 1 closed t phz ; output high to tri-state 0.15 2.0 sc l = 15pf, fig. 34 & 37; s 2 closed receiver delay time between active mode and tri-state mode rs-232/v.28 t pzl ; tri-state to output low 0.12 2.0 sc l = 100pf, fig. 35 & 38; s 1 closed t pzh ; tri-state to output high 0.10 2.0 sc l = 100pf, fig. 35 & 38; s 2 closed t plz ; output low to tri-state 0.10 2.0 sc l = 100pf, fig. 35 & 38; s 1 closed t phz ; output high to tri-state 0.10 2.0 sc l = 100pf, fig. 35 & 38; s 2 closed rs-423/v.10 t pzl ; tri-state to output low 0.10 2.0 sc l = 100pf, fig. 35 & 38; s 1 closed t pzh ; tri-state to output high 0.10 2.0 sc l = 100pf, fig. 35 & 38; s 2 closed t plz ; output low to tri-state 0.10 2.0 sc l = 100pf, fig. 35 & 38; s 1 closed t phz ; output high to tri-state 0.10 2.0 sc l = 100pf, fig. 35 & 38; s 2 closed
6 rev: a date: 1/27/04 sp505 multi?ode serial transceiver ?copyright 2004 sipex corporation power requirements parameter min. typ. max. units conditions v cc 4.75 5.00 5.25 volts i cc (no mode selected) 30 ma all i cc values are with v cc = +5v, (v.28/rs-232) 60 ma t = +25 o c, all drivers are loaded to (v.11/rs-422) 300 ma their specified maximum load and all (rs-449) 250 ma drivers are active at their maximum (v.35) 105 ma specified data transmission rates. eia-530 260 ma eia-530a 250 ma v.36 65 ma other ac characteristics (continued) t a = +25? and v cc = +5.0v unless otherwise noted. parameter min. typ. max. units conditions rs-422/v.11 t pzl ; tri-state to output low 0.10 2.0 sc l = 100pf, fig. 35 & 39; s 1 closed t pzh ; tri-state to output high 0.10 2.0 sc l = 100pf, fig. 35 & 39; s 2 closed t plz ; output low to tri-state 0.10 2.0 sc l = 15pf, fig. 35 & 39; s 1 closed t phz ; output high to tri-state 0.10 2.0 sc l = 15pf, fig. 35 & 39; s 2 closed v.35 t pzl ; tri-state to output low 0.10 2.0 sc l = 100pf, fig. 35 & 39; s 1 closed t pzh ; tri-state to output high 0.10 2.0 sc l = 100pf, fig. 35 & 39; s 2 closed t plz ; output low to tri-state 0.10 2.0 sc l = 15pf, fig. 35 & 39; s 1 closed t phz ; output high to tri-state 0.10 2.0 sc l = 15pf, fig. 35 & 39; s 2 closed transceiver to transceiver skew (per figures 33, 36, 38) v.28 driver 100 ns | (t phl ) tx1 ?(t phl ) tx6,7 | 100 ns | (t plh ) tx1 ?(t plh ) tx6,7 | v.28 receiver 20 ns | (t phl ) rx1 ?(t phl ) rx2,7 | 20 ns | (t phl ) rx1 ?(t phl ) rx2,7 | v.11 driver 2 ns | (t phl ) tx1 ?(t phl ) tx6,7 | 2ns| (t plh ) tx1 ?(t plh ) tx6,7 | v.11 receiver 3 ns | (t phl ) rx1 ?(t phl ) rx2,7 | 3ns| (t phl ) rx1 ?(t phl ) rx2,7 | v.10 driver 5 ns | (t phl ) tx2 ?(t phl ) tx3,4,5 | 5ns| (t plh ) tx2 ?(t plh ) tx3,4,5 | v.10 receiver 5 ns | (t phl ) rx2 ?(t phl ) rx3,4,5 | 5ns| (t phl ) rx2 ?(t phl ) rx3,4,5 | v.35 driver 4 ns | (t phl ) tx1 ?(t phl ) tx6,7 | 4ns| (t plh ) tx1 ?(t plh ) tx6,7 | v.35 receiver 6 ns | (t phl ) rx1 ?(t phl ) rx2,7 | 6ns| (t phl ) rx1 ?(t phl ) rx2,7 |
7 rev: a date: 1/27/04 sp505 multi?ode serial transceiver ?copyright 2004 sipex corporation a v oc c a v t c 3k ? ? oscilloscope scope used for slew rate measurement. a i sc c a c v cc = 0v 2v i x a c 3k ? 2500pf oscilloscope figure 1. v.28 driver output open circuit voltage figure 2. v.28 driver output loaded voltage figure 3. v.28 driver output slew rate figure 4. v.28 driver output short-circuit current figure 6. v.28 driver output rise/fall times figure 5. v.28 driver output power-off impedance test circuits...
8 rev: a date: 1/27/04 sp505 multi?ode serial transceiver ?copyright 2004 sipex corporation figure 7. v.28 receiver input impedance a c i ia 15v a c v oc figure 8. v.28 receiver input open circuit bias a v oc 3.9k ? c a v t 450 ? c a c 0.25v v cc = 0v i x a i sc c figure 9. v.10 driver output open-circuit voltage figure 10. v.10 driver output test terminated voltage figure 12. v.10 driver output power-off current figure 11. v.10 driver output short-circuit current
9 rev: a date: 1/27/04 sp505 multi?ode serial transceiver ?copyright 2004 sipex corporation figure 13. v.10 driver output transition time figure 14. v.10 receiver input current a 450 ? c oscilloscope a c i ia 10v +3.25ma ?.25ma +10v +3v ?v ?0v maximum input current v ersus voltage v .10 receiver figure 15. v.10 receiver input iv graph figure 16. v.11 and v.35 driver output open-circuit voltage a b v oc 3.9k ? v oca v ocb c a b v t 50 ? v os c 50 ? a b c i sa i sb figure 17. v.11 driver output test terminated voltage figure 18. v.11 driver output short-circuit current
10 rev: a date: 1/27/04 sp505 multi?ode serial transceiver ?copyright 2004 sipex corporation a b c i xa 0.25v a b c i xb 0.25v v cc = 0v v cc = 0v a b c i ia 10v c i ib 10v a b +3.25ma ?.25ma +10v +3v ?v ?0v maximum input current v ersus voltage v .11 receiver figure 19. v.11 driver output power-off current figure 20. v.11 receiver input current figure 21. v.11 driver output rise/fall time figure 22. v.11 receiver input iv graph a b 50 ? c 50 ? 50 ? v e oscilloscope
11 rev: a date: 1/27/04 sp505 multi?ode serial transceiver ?copyright 2004 sipex corporation a b c i ia 6v c i ib 6v a b 100 ? to 150 ? 100 ? to 150 ? v .11 receiver w/ optional cable termination (100 ? to 150 ? ) i [ma] = v [v] / 0.1 i [ma] = (v [v] ?3) / 4.0 i [ma] = (v [v] ?3) / 4.0 figure 23. v.11 receiver input current w/ termination figure 24. v.11 receiver input graph w/ termination figure 25. v.35 driver output test terminated voltage figure 26. v.35 driver output offset voltage figure 27. v.35 driver output source impedance a b 50 ? c 50 ? v t v os a b v 2 50 ? c 24khz, 550mv p-p sine wave v 1 a b 50 ? c 50 ? v t v os
12 rev: a date: 1/27/04 sp505 multi?ode serial transceiver ?copyright 2004 sipex corporation figure 32. driver output leakage current test figure 33. driver/receiver timing test circuit figure 30. v.35 receiver input source impedance figure 29. v.35 driver output rise/fall time figure 31. v.35 receiver input short-circuit impedance figure 28. v.35 driver output short-circuit impedance a b c i sc 2v a b c 50 ? oscilloscope 50 ? 50 ? a b c i sc 2v c l1 15pf r out a b a b t in c l2 f in (50% duty cycle, 2.5v p-p ) a b v 2 50 ? c 24khz, 550mv p-p sine wave v 1 a b i zsc logic ? 15v 0 00 0 dec 3 dec 2 dec 1 dec 0 v cc = +5v v cc any one of the two conditions for disabling the driver.
13 rev: a date: 1/27/04 sp505 multi?ode serial transceiver ?copyright 2004 sipex corporation figure 34. driver timing test load circuit figure 35. receiver timing test load circuit 500 ? c l output under t est s 1 s 2 v cc 1k ? 1k ? c rl receiver output s 1 s 2 t est point v cc figure 36. driver propagation delays figure 37. driver enable and disable times +3v 0v dec x 5v v ol a, b 0v 1.5v 1.5v t zl t zh f = 1mhz; t r 10ns; t f 10ns v oh a, b 2.3v 2.3v t lz t hz 0.5v 0.5v output normally low output normally high tx enable figure 38. receiver propagation delays +3v 0v driver input b a driver output v o + differential output v a ?v b 0v v o 1.5v 1.5v t plh t r t f f > 5mhz; t r < 10ns; t f < 10ns v o 1/2v o 1/2v o t phl t dplh t dphl t skew = | t dplh - t dphl | v oh v ol receiver out (v oh - v ol )/2 (v oh - v ol )/2 t plh f > 5mhz; t r < 10ns; t f < 10ns output v 0d2 + v 0d2 a b 0v 0v t phl input t skew = | t phl - t plh |
14 rev: a date: 1/27/04 sp505 multi?ode serial transceiver ?copyright 2004 sipex corporation figure 39. receiver enable and disable times +3v 0v dec x 5v 0v 1.5v 1.5v t zl t zh f = 1mhz; t r 10ns; t f 10ns receiver out 1.5v 1.5v t lz t hz 0.5v 0.5v output normally low output normally high v il v ih receiver out rcvr enable +3v 0v dec x or tx_enable 1.5v 1.5v t zl f = 60khz; t r < 10ns; t f < 10ns t out t lz output low 0v +3v 0v v oh 1.5v 1.5v t zh f = 60khz; t r < 10ns; t f < 10ns t out v oh ?.5v t hz output high 0v dec x or tx_enable v oh ?.5v v ol ?.5v v ol ?.5v v ol figure 40. v.28 (rs-232) and v.10 (rs-423) driver enable and disable times
15 rev: a date: 1/27/04 sp505 multi?ode serial transceiver ?copyright 2004 sipex corporation figure 41. typical v.28 driver output waveform figure 42. typical v.10 driver output waveform - 0v - 0v - 0v - 0v - 0v - 0v - 0v - 0v figure 43. typical v.11 driver output waveform figure 44. typical v.35 driver output waveform input output input a out b out diff out
16 rev: a date: 1/27/04 sp505 multi?ode serial transceiver ?copyright 2004 sipex corporation pinout pin assignments clock and data group pin 1 ?rxd ?receive data; ttl output, sourced from rd(a) and rd(b) inputs. pin 14 ?txd ?ttl input ; transmit data source for sd(a) and sd(b) outputs. pin 15 ?txc ?transmit clock; ttl input for tt driver outputs. pin 20 rxc ?receive clock; ttl output sourced from rt(a) and rt(b) inputs. pin 22 ?st ?send timing; ttl input; source for st(a) and st(b) outputs. pin 37 ?rt(a) ?receive timing; analog input, inverted; source for rxc. pin 38 ?rt(b) ?receive timing; analog input, non-inverted; source for rxc. pin 42 ?st(a) ?send timing; analog output, inverted; sourced from st. pin 44 ?st(b) ?send timing; analog output, non-inverted; sourced from st. pin 59 ?sd(b) ?analog out ?send data, non-inverted; sourced from txd. pin 61 ?sd(a) ?analog out ?send data, inverted; sourced from txd. pin 63 tt(a) analog out terminal timing, inverted; sourced from txc pin 65 ?tt(b) analog out terminal timing, non?nverted; sourced from txc. pin 70 ?rd(a) ?receive data, analog input; inverted; source for rxd. pin 71 ?rd(b) ?receive data; analog input; non-inverted; source for rxd. pin 76 ?sct(a) ?serial clock transmit; analog input, inverted; source for sct. pin 77 ?sct(b) ?serial clock transmit: analog input, non?nverted; source for sct pin 79 ?sct ?serial clock transmit; ttl output; sources from sct(a) and sct(b) inputs. control line group pin 13 ?dtr ?data terminal ready; ttl input; source for tr(a) and tr(b) outputs. pin 16 ?rts ?ready to send; ttl input; source for rs(a) and rs(b) outputs. pin 17 ?rl ?remote loopback; ttl input; source for rl(a) and rl(b) outputs. pin 19 ?dcd?data carrier detect; ttl output; sourced from rr(a) and rr(b) inputs. pin 21 ?ri ?ring in; ttl output; sourced from ic(a) and ic(b) inputs. pin 24 ?ll ?local loopback; ttl input; source for ll(a) and ll(b) outputs. pin 35 ?rr(a)?receiver ready; analog input, inverted; source for dcd. pin 36 ?rr(b)?receiver ready; analog input, non-inverted; source for dcd. pin 39 ?ic(a)?incoming call; analog input, inverted; source for ri. pin 40 ?ic(b)?incoming call; analog input,non-inverted; source for ri. rxd 1 sden 2 tren 3 rsen 4 llen 5 tten 6 scten 7 latch 8 dec 3 9 dec 2 10 dec 1 11 dec 0 12 dtr 13 txd 14 txc 15 r ts 16 rl 17 rlen 18 dcd 19 rxc 20 ri 21 st 22 sten 23 ll 24 v cc 25 c 1 + 26 v dd 27 c 2 + 28 gnd 29 c 1 30 c 2 31 v ss 32 v cc 33 gnd 34 rr(a) 35 rr(b) 36 r t(a) 37 r t(b) 38 ic(a) 39 ic(b) 40 60 gnd 59 sd(b) 58 tr(a) 57 gnd 56 tr(b) 55 v cc 54 rs(a) 53 gnd 52 rs(b) 51 ll(a) 50 gnd 49 ll(b) 48 v cc 47 rl(a) 46 gnd 45 rl(b) 44 st(b) 43 gnd 42 st(a) 41 v cc 80 cts 79 sct 78 dsr 77 sct(b) 76 sct(a) 75 gnd 74 v cc 73 v cc 72 gnd 71 rd(b) 70 rd(a) 69 dm(b) 68 dm(a) 67 cs(b) 66 cs(a) 65 tt(b) 64 gnd 63 tt(a) 62 v cc 61 sd(a) sp505
17 rev: a date: 1/27/04 sp505 multi?ode serial transceiver ?copyright 2004 sipex corporation pin 7 ?scten ?enables sct receiver; active high; ttl input. pin 8 ?latch ?latch control for decoder bits (pins 9-12), active low. logic high input will make decoder transparent. pins 12? ?dec 0 ?dec 3 ?transmitter and receiver decode register; configures transmitter and receiver modes; ttl inputs. pin 18 ?rlen ?enables rl driver; active low; ttl input. pin 23 ?sten ?enables st driver; active low; ttl input. power supplies pins 25, 33, 41, 48, 55, 62, 73, 74 ?v cc ?+5v input. pins 29, 34, 43, 46, 50, 53, 57, 60, 64, 72, 75 gnd ?ground. pin 27 ?v dd +10v charge pump capacitor connects from v dd to v cc . suggested capaci- tor size is 22 f, 16v. pin 32 ?v ss ?0v charge pump capacitor connects from ground to v ss . suggested ca- pacitor size is 22 f, 16v. pins 26 and 30 ?c 1 + and c 1 ?charge pump capacitor ?connects from c 1 + to c 1 . sug- gested capacitor size is 22 f, 16v. pins 28 and 31 ?c 2 + and c 2 ?charge pump capacitor ?connects from c 2 + to c 2 . sug- gested capacitor size is 22 f, 16v. pin 45 ?rl(b) ?remote loopback; analog output, non-inverted; sourced from rl. pin 47 ?rl(a) ?remote loopback; analog output inverted; sourced from rl. pin 49?ll(b) ?local loopback; analog output, non-inverted; sourced from ll. pin 51 ?ll(a) ?local loopback; analog output, inverted; sourced from ll. pin 52 ?rs(b) ?ready to send; analog output, non-inverted; sourced from rts. pin 54 rs(a) ?ready to send; analog output, inverted; sourced from rts. pin 56 tr(b) ?terminal ready; analog output, non-inverted; sourced from dtr. pin 58 ?tr(a) ?terminal ready; analog output, inverted; sourced from dtr. pin 66 cs(a)? clear to send; analog input, inverted; source for cts. pin 67 ?cs(b)?clear to send; analog input, non-inverted; source for cts. pin 68 dm(a)?data mode; analog input, inverted; source for dsr. pin 69 ?dm(b)?data mode; analog input, non-inverted; source for dsr pin 78 ?dsr?data set ready; ttl output; sourced from dm(a), dm(b) inputs. pin 80 cts?clear to send; ttl output; sourced from cs(a) and cs(b) inputs. control registers pins 2 ?sden ?enables txd driver, active low; ttl input. pins 3 ?tren ?enables dtr driver, active low; ttl input. pins 4 ?rsen ?enables rts driver, active low; ttl input. pins 5 ?llen ?enables ll driver, active low; ttl input. pin 6 ?tten ?enables tt driver, active low; ttl input.
18 rev: a date: 1/27/04 sp505 multi?ode serial transceiver ?copyright 2004 sipex corporation a typical +10v charge pump would require external clamping such as 5v zener diodes on v dd and v ss to ground. the +5v output has symmetrical levels as in the +10v output. the +5v is used in the following modes where rs- 423 (v.10) are used: rs-449, eia-530, eia- 530a and v.36. phase 1 (?0v) ?v ss charge storage ?during this phase of the clock cycle, the positive side of capacitors c 1 and c 2 are initially charged to +5v. c l + is then switched to ground and the charge on c 1 is transferred to c 2 . since c 2 + is connected to +5v, the voltage potential across capacitor c 2 is now 10v. phase 1 (?v) ?v ss & v dd charge storage and transfer with the c 1 and c 2 capacitors initially charged to +5v, c l + is then switched to ground and the charge on c 1 is transferred to the v ss storage capacitor. simultaneously the c 2 is switched to ground and 5v charge on c 2 + is transferred to the v dd storage capacitor. features the sp505 is a highly integrated serial trans- ceiver that allows software control of its inter- face modes. similar to the sp504, the sp505 offers the same hardware interface modes for rs-232 (v.28), rs-422a (v.11), rs-449, rs- 485, v.35, eia-530 and includes v.36 and eia- 530a. the interface mode selection is done via a 4?it switch for the drivers and receivers. the sp505 is fabricated using low?ower bicmos process technology, and incorporates a sipex patented (5,306,954) charge pump allowing +5v only operation. each device is packaged in an 80?in jedec quad flatpack package. the sp505 is ideally suited for wide area net- work connectivity based on the interface modes offered and the driver and receiver configura- tions. the sp505 has seven (7) independent drivers and seven (7) independent receivers. in v.35 mode, the sp505 includes the necessary components and termination resistors internal within the device for compliant v.35 operation. theory of operation the sp505 is made up of five separate circuit blocks ?the charge pump, drivers, receivers, decoder and switching array. each of these circuit blocks is described in more detail below. charge?ump the sp505 charge pump is based on the sp504 design where sipex's patented charge pump design (5,306,954) uses a four?hase voltage shifting technique to attain symmetrical 10v power supplies. the charge pump still requires external capacitors to store the charge. in addi- tion the sp504 charge pump supplies +10v or +5v on v ss and v dd depending on the mode of operation. there is a free?unning oscillator that controls the four phases of the voltage shifting. a description of each phase follows. the sp505 charge pump is used for rs-232 where the output voltage swing is typically +10v and also used for rs-423. however, rs- 423 requires the voltage swing on the driver output be between +4v to +6v during an open- circuit (no load). the charge pump would need to be regulated down from +10v to +5v. v cc = +5v ?v ?v +5v v dd storage capacitor c 1 c 2 c 4 + ++ v ss storage capacitor c 3 + figure 46. charge pump phase 1 for +5v. v cc = +5v +5v v dd storage capacitor c 1 c 2 c 4 + ++ v ss storage capacitor c 3 + ?v figure 45. charge pump phase 1 for +10v.
19 rev: a date: 1/27/04 sp505 multi?ode serial transceiver ?copyright 2004 sipex corporation phase 2 (?0v) ?v ss transfer ?phase two of the clock con- nects the negative terminal of c 2 to the v ss storage capacitor and the positive terminal of c 2 to ground, and transfers the generated ?0v or the generated ?v to c 3 . simultaneously, the positive side of capacitor c 1 is switched to +5v and the negative side is connected to ground. phase 2 (?v) ?v ss & v dd charge storage ?c 1 + is recon- nected to v cc to recharge the c 1 capacitor. c 2 + is switched to ground and c 2 is connected to c 3 . the 5v charge from phase 1 is now transferred to the v ss storage capacitor. v ss receives a continuous charge from either c 1 or c 2 . with the c1 capacitor charged to 5v, the cycle begins again. phase 3 ?v dd charge storage ?the third phase of the clock is identical to the first phase ?the charge transferred in c 1 produces ?v in the negative terminal of c 1 , which is applied to the negative side of capacitor c 2 . since c 2 + is at +5v, the voltage potential across c 2 is l0v. for the 5v output, c 2 + is connected to ground so that the potential on c 2 is only +5v. phase 4 ?v dd transfer ?the fourth phase of the clock connects the negative terminal of c 2 to ground and transfers the generated l0v or the generated 5v across c 2 to c 4 , the v dd storage capacitor. again, simultaneously with this, the positive side of capacitor c 1 is switched to +5v and the negative side is connected to ground, and the cycle begins again. since both v dd and v ss are separately gener- ated from v cc in a no?oad condition, v dd and v ss will be symmetrical. older charge pump approaches that generate v from v + will show a decrease in the magnitude of v compared to v + due to the inherent inefficiencies in the design. the clock rate for the charge pump typically operates at 15khz. the external capacitors must be a minimum of 22 f with a 16v breakdown rating. external power supplies for applications that do not require +5v only, external supplies can be applied at the v+ and v pins. the value of the external supply volt- ages must be no greater than +l0.5v. the toler- ance should be +5% from +10v. the current drain for the supplies is used for rs-232 and rs- 423 drivers. for the rs-232 driver, the current requirement will be 3.5ma per driver. the rs- 423 driver worst case current drain will be 11ma per driver. power sequencing is required for the sp505. the supplies must be sequenced accordingly: +10v, +5v and ?0v. it is impor- tant to prevent v ss from starting up before v cc or v dd . figure 47. charge pump phase 2 for +10v. figure 49. charge pump phase 3. v cc = +5v ?0v v dd storage capacitor c 1 c 2 c 4 + ++ v ss storage capacitor c 3 + v cc = +5v ?v ?v +5v v dd storage capacitor c 1 c 2 c 4 + ++ v ss storage capacitor c 3 + figure 50. charge pump phase 4. figure 48. charge pump phase 2 for +5v. v cc = +5v v dd storage capacitor c 1 c 2 c 4 + ++ v ss storage capacitor c 3 + ?v v cc = +5v +10v v dd storage capacitor c 1 c 2 c 4 + ++ v ss storage capacitor c 3 +
20 rev: a date: 1/27/04 sp505 multi?ode serial transceiver ?copyright 2004 sipex corporation requirements of ?.5v minimum differential output levels with a 54 ? load. the driver is designed to operate over a common mode range of +12v to -7v, which follows the rs-485 specification. this also covers the +7v to -7v common mode range for v.11 (rs-422) re- quirements. the v.11 drivers are used in rs- 449, eia-530, eia-530a and v.36 modes as category i signals which are used for clock and data signals. v.35 drivers the fourth type of driver is the v.35 driver. these drivers were specifically designed to com- ply with the requirements of v.35. unique to the industry, the sipex's v.35 driver architec- ture used in the sp505 does not need external termination resistors to operate and comply with v.35. this simplifies existing v.35 implemen- tations that use external termination schemes. the v.35 drivers can produce +0.55v driver output signals with minimum deviation (maxi- mum 20%) given an equivalent load of 100 ? . with the help of internal resistor networks, the drivers achieve the 50 ? to 150 ? source imped- ance and the 135 ? to 165 ? short-circuit imped- ance for v.35. the v.35 driver is disabled and transparent when the decoder is in all other modes. all of the differential drivers; v.11 (rs- 422) and v.35, can operate over 10mbps. driver enable and input all the drivers in the sp505 contain individual enable lines which can tri-state the driver out- puts when a logic "1" is applied. this simplifies half-duplex configurations for some applica- tions and also provides simpler dte/dce flexibility with one integrated circuit. the driver inputs are both ttl or cmos compatible. each driver input should have a pull-down or pull-up resistor so that the output will be at a defined state. unused driver inputs should not be left floating. receivers the sp505 has seven (7) independent receivers which can be programmed for the different interface modes. control for the mode selection is done via a 4?it control word, which is the same as the driver's 4-bit control word. like the drivers, the receivers are prearranged for the specific requirements of the synchronous drivers the sp505 has seven (7) enhanced independent drivers. control for the mode selection is done via a four?it control word. the drivers are prearranged such that for each mode of opera- tion, the relative position and functionality of the drivers are set up to accommodate the se- lected interface mode. as the mode of the driv- ers is changed, the electrical characteristics will change to support the requirements of clock, data, and control line signal levels. table 1 shows the mode of each driver in the different interface modes that can be selected. there are four basic types of driver circuits v.28, v.11, v.10 and v.35. v.28 drivers the v.28 drivers output single?nded signals with a minimum of +5v (with 3k ? & 2500pf loading), and can operate to at least 120kbps under full load. since the sp505 uses a charge pump to generate the rs-232 output rails, the driver outputs will never exceed +10v. the v.28 drivers are used in rs-232 mode for all signals, and also in v.35 mode where four (4) drivers are used as the control line signals (dtr, rts, ll, and rl). v.10 drivers the v.10 (rs-423) drivers are also single ended signals which produce open circuit v ol and v oh measurements of +4.0v to +6.0v. when terminated with a 450 ? load to ground, the driver output will not deviate more than 10% of the open circuit value. this is in compliance of the itu v.10 specification. the v.10 drivers are used in rs-449, eia-530, eia-530a and v.36 modes as category ii signals from each of their corresponding specifications. v.11 drivers the third type of driver is a v.11 (rs-422) type differential driver. due to the nature of differ- ential signaling, the drivers are more immune to noise as opposed to single-ended transmission methods. the advantage is evident over high speeds and long transmission lines. the strength of the driver outputs can produce differential signals that can maintain typically +2.2v differ- ential output levels with a load of 100 ? . the signal levels and drive capability of these driv- ers allow the drivers to also support rs-485
21 rev: a date: 1/27/04 sp505 multi?ode serial transceiver ?copyright 2004 sipex corporation serial interface. as the operating mode of the receivers is changed, the electrical characteris- tics will change to support the requirements of clock, data, and control line receivers. table 2 shows the mode of each receiver in the different interface modes that can be selected. there are three basic types of receiver circuits ?v.28, v.10, and v.11. v.28 receivers the v.28 receiver is single?nded and accepts v.28 signals from the v.28 driver. the v.28 receiver has an operating voltage range of +15v and can receive signals down to +3v. the input sensitivity complies with rs-232 and v.28 speci- fications at +3v. the input impedance is 3k ? to 7k ? in accordance to rs-232 and v.28 over a +15v input range. the receiver output pro- duces a ttl/cmos signal with a +2.4v mini- mum for a logic "1" and a +0.8v maximum for a logic "0". v.28 receivers are used in rs-232 mode for all data, clock and control signals. they are also used in v.35 mode for control line signals: cts, dsr, ll, and rl. the v.28 receivers can operate to at least 120kbps. v.10 receivers the v.10 receivers are also single?nded as with the v.28 receivers but have an input thresh- old as low as +200mv. the input impedance is guaranteed to be greater than 4k ? , with an operating voltage range of +7v. the v.10 re- ceivers can operate to at least 120kbps. v.10 receivers are used in rs-449, eia-530, eia- 530a and v.36 modes as category ii signals as indicated by their corresponding specifications. v.11 receivers the third type of receiver is a differential which supports v.11 and rs-485 signals. this re- ceiver has a typical input impedance of 10k ? and a typical differential threshold of +200mv, which complies with the v.11 specification. since the characteristics of the v.11 receivers are actually subsets of rs-485, the v.11 receiv- ers can accept rs-485 signals. however, these receivers cannot support 32-transceivers on the signal bus due to the lower input impedance as specified in the rs-485 specification. three receivers (rxd, rxc, and sct) include a typi- cal 120 ? cable termination resistor across the a and b inputs. the resistor for the three receivers is switched on when the sp505 is configured in a mode which uses v.11 receivers. the v.11 cable termination resistor is switched off when the receiver is disabled or in another operating mode not using v.11 receivers. the v.11 re- ceivers are used in x.21, rs-449, eia-530, eia-530a and v.36 as category i signals for receiving clock, data, and some control line signals not covered by category ii v.10 circuits. the differential receivers can receive signals over 10mbps. v.35 receiver the v.11 receivers are also used for the v.35 mode. unlike the older implementations of differential receivers used for v.35, the sp505 contains an internal resistor termination net- work that ensures a v.35 input impedance of 100 ? ( +10 ? ) and a short-circuit impedance of 150 ? ( +15 ? ). the traditional v.35 implemen- tations required external termination resistors to achieve the proper v.35 impedances. the inter- nal network is connected via low on-resistance fet switches when the decoder is changed to v.35 mode. these fet switches can accept input signals of up to +15v without any forward biasing and other parasitic affects. the v.35 termination resistor network is switched off when the receiver is disabled either by the de- coder or receiver enable pin. the termination network is transparent when all other modes are selected. the v.35 receivers can operate over 10mbps. receiver enable and output only one receiver includes an enable line. the scten input for the sct receiver can enable or tri-state the output of the receiver. when the pin is at a logic "0", the receiver output is high impedance and any input termination internal connected is switched off. the inputs will be at approximately 10k ? during tri-state. v .11 termination mode [0100] v .35 mode r in [a] r in [b] to non-inverting input of receiver to inverting input of receiver r on = 20 ? r on = 1 ? 51 ? 51 ? 124 ? r on = 1 ? figure 51. simplified r in termination circuit
22 rev: a date: 1/27/04 sp505 multi?ode serial transceiver ?copyright 2004 sipex corporation all receivers include a fail-safe feature that outputs a logic "1" when the receiver inputs are open. the differential receivers allocated for data and clock signals (rxd, rxc, and sct) have advanced fail-safe that outputs a logic "1" when the inputs are either open, shorted, or terminated. other discrete or integrated imple- mentations require external pull-up and pull- down resistors to define the receiver output state. for single-ended v.28 receivers, there are internal 5k ? pull-down resistors on the inputs which produces a logic high ("1") at the receiver outputs. the single-ended v.10 receivers pro- duce a logic low ("0") on the output when the inputs are open. this is due to an internal pull- up device connected to the input. the differen- tial receivers have the same internal pull-up device on the non-inverting input which pro- duces a logic high ("1") at the receiver output, representing an "off" state to the hdlc con- troller. the three differential receivers when configured in v.35 mode (rxd, rxc & sct) will also include fail-safe even when the internal termination resistor network is connected and the inputs are either shorted or floating. decoder the sp505 has the ability to change the inter- face mode of the drivers or receivers via a 4?it switch. the decoder for the drivers and receiv- ers can be latched through a control pin. the control word can be latched either high or low to write the appropriate code into the sp505 . the codes shown in tables 1 and 2 are the only specified, valid modes for the sp505 . unde- fined codes may represent other interface modes not specified (consult the factory for more infor- mation). the drivers and receivers are con- trolled with the data bits labeled dec 3 ?ec 0 . all of the drivers outputs and receiver outputs can be put into tri-state mode by writing 0000 to the driver decode switch. all internal termina- tion networks are switched off during this mode. individual tri-state capability is possible for all drivers through each driver's own enable control input. the sct receiver also contains an indi- vidual enable input. when this control pin is disabled (logic "0"), the v.11 and v.35 input termination is deactivated. the 0000 decoder word will override the enable control line for the one receiver (sct). the sp505 contains internal loopback capabili- ties for self-diagnostic tests. loopback is en- abled through the decoder. to initiate single- ended mode loopback, the decoder word is 1010. to initiate differential mode loopback, the de- coder word is 1011. the minimum transmission rates into the sp505 under loopback conditions are 120kbps for single-ended mode and 5mbps for differential mode. the driver outputs are tri- stated and the receiver inputs are disabled dur- ing loopback. the receiver input impedance during loopback is approximately 10k ? . the sp505 is equipped with a latch control for the four (4) decoder bits. the latch control pin is pin 8 of the sp505 . the latch control is active low, a logic low on pin 8 will latch the decoder signals. a logic "1" on pin 8 will force the latch to be transparent to the user. a pulse width of at least 30ns is required to latch the decoder for the next mode. the resultant output is typically 600ns after the latch control pin is toggled assuming that the decoder word is set. net1/2 & tbr2 european compliancy as with all of sipex's previous multi-protocol serial transceiver ics, the drivers and receivers have been designed to meet all the requirements to net1/2. the sp505 is internally tested to all the net1/2 physical layer testing parameters and the itu series v specifications. with the emergence of etsi tbr2 (technical basis for regulation) document now in place as an alternative for european compliancy, sipex has tested the sp505 to tbr2 specifications to ensure "ce" approval for either testing method. the sp505 was externally tested by tuv telecom services, division of tuv rheinland, and passed both net1/2 and tbr2 require- ments. test reports (net2/052101/98 for net1/2 and ctr2/ 05101/98 for tbr2) can be furnished upon request. please note that although the sp505 adheres to net1/2 testing; any complex or unusual con- figuration should be double-checked to ensure net compliance. consult factory for details.
23 rev: a date: 1/27/04 sp505 multi?ode serial transceiver ?copyright 2004 sipex corporation sp505 receiver mode selection sp505 driver mode selection pin label rd(a) rd(b) r t(a) r t(b) cs(a) cs(b) dm(a) dm(b) rr(a) rr(b) ic(a) ic(b) sct(a) sct(b) pin label mode: rs232 v.35 rs422 rs449 eia530 eia-530a v.36 0000 0010 1110 0100 0101 1100 1101 1111 0110 sd(a) tri-state v .28 v .35 v .11 v .11 v .11 sd(b) v .35+ v .11+ v .11+ v .11+ tr(a) tri-state v .28 v .11 v .11 v .11 v .10 tr(b) tri-state tri-state tri-state v .11+ v .11+ v .11+ tri-state rs(a) tri-state v .28 v .11 v .11 v .11 rs(b) tri-state tri-state tri-state v .11+ v .11+ v .11+ rl(a) tri-state v .28 v .11 v .11 v .10 rl(b) tri-state tri-state tri-state v .11+ v .11+ tri-state ll(a) tri-state v .28 v .11 v .11 v .10 ll(b) tri-state tri-state tri-state v .11+ v .11+ tri-state st(a) tri-state v .28 v .35 v .11 v .11 v .11 st(b) v .35+ v .11+ v .11+ v.11+ tt(a) tri-state v .28 v .35 v .11 v .11 v .11 tt(b) v .35+ v .11+ v .11+ v .11+ tri-state tri-state tri-state tri-state tri-state tri-state v .28 v .28 v .28 v .28 v .11 v .11+ v .11 v .11+ v .11 v .11+ tri-state v .11 v .11+ v .11 v .11+ v .10 v .11 v .11+ v .11 v .11+ v .11 v .11+ v .11 v .11+ v .11 v .11+ v .10 tri-state v .10 tri-state v .11 v .11+ v .10 tri-state v .10 tri-state v .10 tri-state v .11 v .11+ v .11 v .11+ mode: rs232 v.35 rs422 w/ term. rs422 rs449 eia530 eia-530a v.36 0000 0010 1110 0100 0101 1100 1101 1111 0110 v .28 v .35 v .11 v .11 v .11 v .35+ v .11+ v .11+ v .11+ v .28 v .11 v .11 v .11 v .11+ v .11+ v .11+ v .28 v .11 v .11 v .11 v .11+ v .11+ v .11+ v .28 v .11 v .11 v .11+ v .11+ v .28 v .11 v .11 v .11+ v .11+ v .28 v .11 v .11 v .11+ v .11+ v .28 v .35 v .11 v .11 v .11 v .35+ v .11+ v .11+ v .11+ v .28 v .28 v .28 v .11 v .11+ v .11 v .11+ v .11 v .11+ v .10 v .10 v .10 >10k ? to gnd >10k ? to gnd >10k ? to gnd >10k ? to gnd >10k ? to gnd >10k ? to gnd >10k ? to gnd >10k ? to gnd >10k ? to gnd >10k ? to gnd >10k ? to gnd >10k ? to gnd >10k ? to gnd >10k ? to gnd >10k ? to gnd >10k ? to gnd >10k ? to gnd >12k ? to gnd >10k ? to gnd >10k ? to gnd >10k ? to gnd >10k ? to gnd >10k ? to gnd >10k ? to gnd >10k ? to gnd >10k ? to gnd >10k ? to gnd v .11 v .11+ v .11 v .11+ >10k ? to gnd >10k ? to gnd v .10 v .10 >10k ? to gnd v .10 >10k ? to gnd v .10 v .11 v .11+ v .11 v .11+ v .11 v .11+ >10k ? to gnd v .10 v .35 v .35+ v .28 >10k ? to gnd v .11 v .11+ 30 dec ?dec 30 dec ?dec 120 ? 120 ? 120 ? rs422 w/ term. 120 ? 120 ? 120 ? v .11 v .11+ v .11 v .11+ 120 ? 120 ? 120 ? v .11 v .11+ v .11 v .11+ v .11 v .11+ 120 ? 120 ? 120 ? v .11 v .11+ v .11 v .11+ v .11 v .11+ 120 ? 120 ? 120 ? table 1. sp505 driver decoder table table 2. sp505 receiver decoder table
24 rev: a date: 1/27/04 sp505 multi?ode serial transceiver ?copyright 2004 sipex corporation figure 52. sp505 typical operating circuit rd(a) 70 rxd 1 rd(b) 71 r t(a) 37 rxc 20 r t(b) 38 cs(a) 66 cts 80 cs(b) 67 dm(a) 68 dsr 78 dm (b) 69 rr(a) 35 dcd 19 rr(b) 36 ic(a) 39 ri 21 ic(b) 40 sct(a) 76 sct 79 scten 7 sct(b) 77 14 txd 61 sd(a) 59 sd(b) 2 sden 22 st 42 st(a) 44 st(b) 23 sten 15 txc 63 tt(a) 65 tt(b) 6 tten 13 dtr 58 tr(a) 56 tr(b) 3 tren 16 rts 54 rs(a) 52 rs(b) 4 rsen 17 rl 47 rl(a) 45 rl(b) 18 rlen 24 ll 51 ll(a) 49 ll(b) 5 llen 22 f 22 f 1n5819 v cc v dd c1- c2- v ss c1+ c2+ 22 f +5v 10 f 27 25 26 31 28 30 22 f 32 9 10 11 12 mode x 0 1 0 0 rs-422 mode input word a b charge pump a ?receiver tri-state circuitry, v .11, & v.35 termination resistor circuitry (rxd, rxc & sct). b ?driver tri-state circuitry & v .35 termination circuitry (txd, txc & st). sp505 (see pinout assignments for ground pins) 8 decoder latch latch (see pinout for v cc pins)
25 rev: a date: 1/27/04 sp505 multi?ode serial transceiver ?copyright 2004 sipex corporation figure 53. mode diagram ?rs-232 mode: rs-232 (v.28) driver/receiver dec 3 dec 2 dec 1 dec 0 ic(a) 39 ri 21 scten 7 receivers drivers 0 0 1 0 24 ll 51 ll(a) 5 llen 13 dtr 58 tr(a) 3 tren dm(a) 68 dsr 78 16 rts 54 rs(a) 4 rsen 17 rl 47 rl(a) 18 rlen rr(a) 35 dcd 19 cs(a) 66 cts 80 rd(a) 70 rxd 1 r t(a) 37 rxc 20 sct(a) 76 sct 79 14 txd 61 sd(a) 2 sden 15 txc 63 tt(a) 6 tten 22 st 42 st(a) 23 sten
26 rev: a date: 1/27/04 sp505 multi?ode serial transceiver ?copyright 2004 sipex corporation figure 54. mode diagram ?v.35 mode: v.35 driver/receiver dec 3 dec 2 dec 1 dec 0 rd(a) 70 rxd 1 r t(a) 37 rxc 20 ic(a) 39 ri 21 sct(a) 76 sct 79 scten 7 sct(b) 77 15 txc 63 tt(a) 65 tt(b) 6 tten receivers drivers 22 st 42 st(a) 44 st(b) 23 sten r t(b) 38 rd(b) 71 1 1 1 0 24 ll 51 ll(a) 5 llen 14 txd 61 sd(a) 59 sd(b) 2 sden 13 dtr 58 tr(a) 3 tren dm(a) 68 dsr 78 16 rts 54 rs(a) 4 rsen 17 rl 47 rl(a) 18 rlen rr(a) 35 dcd 19 cs(a) 66 cts 80 v .35 ntwk v .35 ntwk v .35 ntwk v .35 ntwk v .35 ntwk v .35 ntwk
27 rev: a date: 1/27/04 sp505 multi?ode serial transceiver ?copyright 2004 sipex corporation figure 55. mode diagram ?rs-422 mode: rs-422 [w/ termination] driver/receiver dec 3 dec 2 dec 1 dec 0 rd(a) 70 rxd 1 r t(a) 37 rxc 20 sct(a) 76 sct 79 scten 7 sct(b) 77 15 txc 63 tt(a) 65 tt(b) 6 tten receivers drivers 22 st 42 st(a) 44 st(b) 23 sten cs(a) 66 cts 80 rr(a) 35 dcd 19 rr(b) 36 cs(b) 67 r t(b) 38 rd(b) 71 0 1 0 0 24 ll 51 ll(a) 49 ll(b) 5 llen 14 txd 61 sd(a) 59 sd(b) 2 sden 13 dtr 58 tr(a) 56 tr(b) 3 tren 16 rts 54 rs(a) 52 rs(b) 4 rsen 17 rl 47 rl(a) 45 rl(b) 18 rlen ic(a) 39 ri 21 ic(b) 40 dm(a) 68 dsr 78 dm(b) 69 120 ? 120 ? 120 ?
28 rev: a date: 1/27/04 sp505 multi?ode serial transceiver ?copyright 2004 sipex corporation figure 56. mode diagram ? rs-449 mode: rs-449 driver/receiver dec 3 dec 2 dec 1 dec 0 rd(a) 70 rxd 1 r t(a) 37 rxc 20 ic(a) 39 ri 21 sct(a) 76 sct 79 scten 7 sct(b) 77 15 txc 63 tt(a) 65 tt(b) 6 tten receivers drivers 22 st 42 st(a) 44 st(b) 23 sten cs(a) 66 cts 80 rr(a) 35 dcd 19 rr(b) 36 cs(b) 67 r t(b) 38 rd(b) 71 1 1 0 0 24 ll 51 ll(a) 5 llen 14 txd 61 sd(a) 59 sd(b) 2 sden 13 dtr 58 tr(a) 56 tr(b) 3 tren 16 rts 54 rs(a) 52 rs(b) 4 rsen dm(a) 68 dsr 78 dm(b) 69 17 rl 47 rl(a) 18 rlen 120 ? 120 ? 120 ?
29 rev: a date: 1/27/04 sp505 multi?ode serial transceiver ?copyright 2004 sipex corporation figure 57. mode diagram ?rs-422 w/o termination mode: rs-422 [no termination] driver/receiver dec 3 dec 2 dec 1 dec 0 rd(a) 70 rxd 1 r t(a) 37 rxc 20 sct(a) 76 sct 79 scten 7 sct(b) 77 15 txc 63 tt(a) 65 tt(b) 6 tten receivers drivers 22 st 42 st(a) 44 st(b) 23 sten cs(a) 66 cts 80 rr(a) 35 dcd 19 rr(b) 36 cs(b) 67 r t(b) 38 rd(b) 71 0 1 0 1 24 ll 51 ll(a) 49 ll(b) 5 llen 14 txd 61 sd(a) 59 sd(b) 2 sden 13 dtr 58 tr(a) 56 tr(b) 3 tren 16 rts 54 rs(a) 52 rs(b) 4 rsen 17 rl 47 rl(a) 45 rl(b) 18 rlen ic(a) 39 ri 21 ic(b) 40 dm(a) 68 dsr 78 dm(b) 69
30 rev: a date: 1/27/04 sp505 multi?ode serial transceiver ?copyright 2004 sipex corporation figure 58. mode diagram ?eia-530 24 ll 51 ll(a) 5 llen 120 ? mode: eia-530 driver/receiver dec 3 dec 2 dec 1 dec 0 rd(a) 70 rxd 1 r t(a) 37 rxc 20 ic(a) 39 ri 21 sct(a) 76 sct 79 scten 7 sct(b) 77 15 txc 63 tt(a) 65 tt(b) 6 tten receivers drivers 22 st 42 st(a) 44 st(b) 23 sten cs(a) 66 cts 80 rr(a) 35 dcd 19 rr(b) 36 cs(b) 67 r t(b) 38 rd(b) 71 1 1 0 1 14 txd 61 sd(a) 59 sd(b) 2 sden 16 rts 54 rs(a) 52 rs(b) 4 rsen 17 rl 47 rl(a) 45 rl(b) 18 rlen dm(a) 68 dsr 78 dm(b) 69 120 ? 120 ? 13 dtr 58 tr(a) 56 tr(b) 3 tren
31 rev: a date: 1/27/04 sp505 multi?ode serial transceiver ?copyright 2004 sipex corporation figure 59. mode diagram ?eia-530a mode: eia-530a driver/receiver dec 3 dec 2 dec 1 dec 0 rd(a) 70 rxd 1 r t(a) 37 rxc 20 ic(a) 39 ri 21 sct(a) 76 sct 79 scten 7 sct(b) 77 15 txc 63 tt(a) 65 tt(b) 6 tten receivers drivers 22 st 42 st(a) 44 st(b) 23 sten cs(a) 66 cts 80 rr(a) 35 dcd 19 rr(b) 36 cs(b) 67 r t(b) 38 rd(b) 71 1 1 1 1 24 ll 51 ll(a) 5 llen 14 txd 61 sd(a) 59 sd(b) 2 sden 16 rts 54 rs(a) 52 rs(b) 4 rsen 17 rl 47 rl(a) 45 rl(b) 18 rlen 13 dtr 58 tr(a) 3 tren dm(a) 68 dsr 78 120 ? 120 ? 120 ?
32 rev: a date: 1/27/04 sp505 multi?ode serial transceiver ?copyright 2004 sipex corporation figure 60. mode diagram ?v.36 mode: v.36 driver/receiver dec 3 dec 2 dec 1 dec 0 rd(a) 70 rxd 1 r t(a) 37 rxc 20 ic(a) 39 ri 21 sct(a) 76 sct 79 scten 7 sct(b) 77 15 txc 63 tt(a) 65 tt(b) 6 tten receivers drivers 22 st 42 st(a) 44 st(b) 23 sten r t(b) 38 rd(b) 71 0 1 1 0 24 ll 51 ll(a) 5 llen 14 txd 61 sd(a) 59 sd(b) 2 sden 13 dtr 58 tr(a) 3 tren dm(a) 68 dsr 78 16 rts 54 rs(a) 4 rsen 17 rl 47 rl(a) 18 rlen rr(a) 35 dcd 19 cs(a) 66 cts 80 120 ? 120 ? 120 ?
33 rev: a date: 1/27/04 sp505 multi?ode serial transceiver ?copyright 2004 sipex corporation loopback mode... the sp505 is equipped with two loopback modes. single-ended loopback internally connects v.28 driver outputs to v.28 receiver inputs. the signal path is non-inverting and will support data rates up to 120kbps. the propaga- tion delay times are as specified in the electrical specifications. to initiate a single-ended loopback, the code "1010" should be written to the driver decoder. differential loopback is implemented by applying "1011" to the driver decoder. this internally connects v.11 driver outputs to v.11 receiver inputs. the signal path again is non-inverting; the differential loopback data rate can be at least 5mbps. under loopback conditions the receiver decoder is disabled. while the sp505 is in either single- ended or differential loopback mode, the driver outputs are tri-stated and the receiver inputs are disabled. mode driver output receiver input driver receiver non-inverting inverting non-inverting inverting input output loopback tri-state tri-state >10k to gnd >10k to gnd active active tri-state tri-state >10k to gnd >10k to gnd active active power down clamped tri-state tri-state >10k to gnd >10k to gnd inactive at ?.6v tri-state tri-state tri-state >10k to gnd >10k to gnd inactive tri-state dec=1010 dec=1011 v cc =v dd =v ss =0v dec=0000 mode: differential loopback driver/receiver dec 3 dec 2 dec 1 dec 0 rd(a) 70 rxd 1 r t(a) 37 rxc 20 sct(a) 76 sct 79 scten 7 sct(b) 77 15 txc 63 tt(a) 65 tt(b) 6 tten receivers drivers 22 st 42 st(a) 44 st(b) 23 sten cs(a) 66 cts 80 rr(a) 35 dcd 19 rr(b) 36 cs(b) 67 r t(b) 38 rd(b) 71 1 0 1 1 24 ll 51 ll(a) 49 ll(b) 5 llen 14 txd 61 sd(a) 59 sd(b) 2 sden 13 dtr 58 tr(a) 56 tr(b) 3 tren 16 rts 54 rs(a) 52 rs(b) 4 rsen 17 rl 47 rl(a) 45 rl(b) 18 rlen ic(a) 39 ri 21 ic(b) 40 dm(a) 68 dsr 78 dm(b) 69 ic(a) 39 ri 21 scten 7 receivers drivers 1 0 1 0 24 ll 51 ll(a) 5 llen 13 dtr 58 tr(a) 3 tren dm(a) 68 dsr 78 16 rts 54 rs(a) 4 rsen 17 rl 47 rl(a) 18 rlen rr(a) 35 dcd 19 cs(a) 66 cts 80 rd(a) 70 rxd 1 r t(a) 37 rxc 20 sct(a) 76 sct 79 14 txd 61 sd(a) 2 sden 15 txc 63 tt(a) 6 tten 22 st 42 st(a) 23 sten mode: single-ended loopback driver/receiver dec 3 dec 2 dec 1 dec 0
34 rev: a date: 1/27/04 sp505 multi?ode serial transceiver ?copyright 2004 sipex corporation 80 pin mqfp (ms-022 bc) b e seating plane a1 a a l1 5 -16 0 min. 0 ? 5 -16 l a2 0.30" rad. typ. 0.20" rad. typ. c pin 1 e1 d1 d c l e c l d2 e2 dimensions minimum/maximum (mm) symbol a a1 a2 b d d1 d2 e e1 e2 e n 80?in mqfp jedec ms-22 (bec) variation min nom max 2.45 0.00 0.25 1.80 2.00 2.20 0.22 0.40 17.20 bsc 14.00 bsc 12.35 ref 17.20 bsc 14.00 bsc 12.35 ref 0.65 bsc 80 common dimentions symbl min nom max c 0.11 23.00 l 0.73 0.88 1.03 l1 1.60 basic package: 80 pin mqfp
35 rev: a date: 1/27/04 sp505 multi?ode serial transceiver ?copyright 2004 sipex corporation ordering information model temperature range package types SP505ACF ........................................................................ 0? to +70? ...................................................... 80?in jedec (be-2 outline) mqfp sp505bcf ........................................................................ 0? to +70? ...................................................... 80?in jedec (be-2 outline) mqfp sipex corporation reserves the right to make changes to any products described herein. sipex does not assume any liability aris ing out of the application or use of any product or circuit described hereing; neither does it convey any license under its patent rights nor the rights of others. corporation analog excellence sipex corporation headquarters and sales office 233 south hillview drive milpitas, ca 95035 tel: (408) 934-7500 fax: (408) 935-7600 sales office 22 linnell circle billerica, ma 01821 tel: (978) 667-8700 fax: (978) 670-9001 e-mail: sales@sipex.com please consult the factory for pricing and availability on a tape-on-reel option. date revision description 1/27/04 a implemented tracking revision. revision history

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